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ksz8081mlx 10base - t/100base - tx physical layer transceiver revision 1.3 linkmd is a registered trademark of micrel, inc. micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1 (408) 944 - 0800 ? fax + 1 (408) 474 - 1000 ? http://www.micrel.com august 19 , 2015 revision 1.3 general description the ksz8081mlx is a single - supply 10base - t/ 100base - tx ethernet physical - layer transceiver for transmission and reception of data over standard cat - 5 unshielded twisted pair (utp) cable. the ksz8081mlx is a highly - integrated, compact solution. it reduces board cost and simplifies board layout by using on - chip termination resistors for the differential pairs, by integrating a low - noise regulator to supply the 1.2v core, and by offering 1.8/2.5/3.3v digital i/o interface support. the ksz8081mlx offers the media independent interface (mii) for direct connection with mii - compliant ethernet mac processors and switches. the ksz8081mlx provides diagnostic features to faci litate system bring - up and debugging in production testing and in product deployment. parametric nand tree support enables fault detection between ksz8081mlx i/os and the board. micrel linkmd ? tdr - based cable diagnostics identify faulty copper cabling. th e ksz8081mlx is available in the 48 - pi n, lead - free lqfp package (see ordering information ). datasheets and support documentation are available on website at: www.micrel.com . features ? single - chip 10base - t/100base - tx ieee 802.3 compliant ethernet transceiver ? mii interface support ? back - to - back mode support for 100mbps copper repeater ? mdc/mdio management interface for phy register configuration ? programmable interrupt output ? led outputs for link, activity, and speed status indication ? on - chip termination resistors for the differential pairs ? baseline wander correction ? hp auto mdi/mdi - x to reliably detect and correct straight - through and crossover cable connections with disable and enable option ? auto - negotiation to automatica lly select the highest link - up speed (10/100mbps) and duplex (half/full) ? power - down and power - saving modes ? linkmd tdr - based cable diagnostics to identify faulty copper cabling ? parametric nand tree support for fault detection between chip i/os and the board ? hbm esd rating (6kv) functional diagram downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 2 revision 1.3 features (continued) ? loopback modes for diagnostics ? single 3.3v power supply with vdd i/o options for 1.8v, 2.5v, or 3.3v ? built - in 1.2v regulator for core ? available in 48 - pin 7mm x 7mm lqfp package applications ? game console s ? ip phone s ? ip set - top box es ? ip tv s ? lom ? printer s ordering information ordering part number temperature range package lead finish description KSZ8081MLXCA 0c to 70c 48 - pin lqfp pb-free mii, commercial temperature . ksz8081mlxia ( 1 ) ? 40c to 85c 48 - pin lqfp pb-free mii, industrial temperature . ksz8081mlx -eval ksz8081mlx evaluation board (mounted with ksz8081mlx device in commercial temperature) note: 1. contact factory for lead time . downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 3 revision 1.3 revision history date summary of changes revision 11/ 5/12 initial release of new product datasheet. 1.0 2/6/14 removed copper - wire bonding part numbers from ordering information. added note for txc (pin 33 ) and register 16h, bit [15] regarding a reserved factory mode. removed txc and rxc clock connections for mii back - to - back mode. this is a datasheet correction. there is no change to the silicon. added series resistance and load capacitance for the crystal selection criteria. 1.1 11/25 /14 added silver - wire bonding part numbers to ordering information. updated ordering information to include ordering part number and device marking. 1.2 08/ 19 /15 update d pin configuration drawing, updated descriptions for pin 44 and nand tree i/o testing section . add max frequency for mdc in mii management (miim) interface section. updated table 14 and table 16. updated ordering information table for silver wire device as normal part number. updated pin 33 txc and register 16h bit [15] description. updated description and add an equation in linkmd section. add a note for t able 18. updated description for figure 18. add a note for figure 19. add hbm esd rating in features. 1.3 downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 4 revision 1.3 contents list of figures .......................................................................................................................................................................... 6 list of tables ........................................................................................................................................................................... 7 pin configurat ion ..................................................................................................................................................................... 8 pin description ........................................................................................................................................................................ 9 strapping options ................................................................................................................................................................ . 12 functional description: 10base - t/100base - tx transceiver ................................................................................................ 14 100base - tx transmit ........................................................................................................................................................ 14 100base - tx receive ......................................................................................................................................................... 14 scrambler/de - scrambler (100base - tx only) ................................................................................................................... 14 10base - t transmit ............................................................................................................................................................ 14 10base - t receive ............................................................................................................................................................. 15 sqe and jabber function (10base - t only) ...................................................................................................................... 15 pll clock synthesizer ...................................................................................................................................................... 15 auto - negotiation ................................................................................................................................................................ 15 mii interface .......................................................................................................................................................................... 17 mii signal definition ........................................................................................................................................................... 17 transmit clock (txc) .................................................................................................................................................... 17 transmit enable (txen) ................................................................................................................................................ 17 transmit data[3:0] (txd[3:0]) ........................................................................................................................................ 18 receive clock (rxc) ..................................................................................................................................................... 18 receive data valid (rxdv) ........................................................................................................................................... 18 receive data[3:0] (rxd[3:0]) ........................................................................................................................................ 18 receive error (rxer) .................................................................................................................................................... 18 carrier sense (crs) ...................................................................................................................................................... 18 collision (col) ............................................................................................................................................................... 18 mii signal diagram ............................................................................................................................................................ 18 back - to - back mode C 100mbps copper repeater ............................................................................................................... 20 mii back - to - back mode ..................................................................................................................................................... 20 mii ma nagement (miim) interface ......................................................................................................................................... 21 interrupt (intrp) ................................................................................................................................................................... 21 hp auto mdi/mdi -x .............................................................................................................................................................. 21 straight cable .................................................................................................................................................................... 22 crossover cabl e ................................................................................................................................................................ 23 loopback mode ..................................................................................................................................................................... 24 local (digital) loopback .................................................................................................................................................... 24 remote (analog) loopback ............................................................................................................................................... 25 linkmd ? cable diagnostic .................................................................................................................................................... 26 usag e ............................................................................................................................................................................. 26 nand tree support .............................................................................................................................................................. 27 nand tree i/o testing ..................................................................................................................................................... 28 power management .............................................................................................................................................................. 29 power - saving mode .......................................................................................................................................................... 29 energy - detect power - down mode .................................................................................................................................... 29 downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 5 revision 1.3 power - down mode ............................................................................................................................................................ 29 slow - oscillator mode ......................................................................................................................................................... 29 referenc e circuit for power and ground connections ......................................................................................................... 30 typical current/power consumption .................................................................................................................................... 31 register map ......................................................................................................................................................................... 33 register description .............................................................................................................................................................. 34 absolute maximum ratings .................................................................................................................................................. 44 operating ratings ................................................................................................................................................................ . 44 electrical characteristics ....................................................................................................................................................... 44 timing diagrams ................................................................................................................................................................... 46 mii sqe timing (10base - t) .............................................................................................................................................. 46 mi i transmit timing (10base - t) ........................................................................................................................................ 47 mii receive timing (10base - t) ......................................................................................................................................... 48 mii transmit timing (100base - tx) ................................................................................................................................... 49 mii receive timing (100base - tx) .................................................................................................................................... 50 auto - negotiation timing .................................................................................................................................................... 51 mdc/mdio timing ............................................................................................................................................................ 52 power - up/reset timing .................................................................................................................................................... 53 reset circuit .......................................................................................................................................................................... 54 reference circuits ? led strap - in pins ................................................................................................................................ 55 reference clock ? connection and selection ...................................................................................................................... 56 magnetic ? connection and selection .................................................................................................................................. 57 package information and recommended land pattern ....................................................................................................... 59 downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 6 revision 1.3 list of figures figure 1. auto - negotiation flow chart ................................................................................................................................ 16 figure 2. ksz8081mlx mii interface ................................................................................................................................ . 19 figure 3. ksz8081mlx to ksz8081mlx back - to - back copper repeater ........................................................................ 20 figure 4. typical straight cable connection ...................................................................................................................... 22 figure 5. typical crossover cable connec tion .................................................................................................................. 23 figure 6. local (digital) loopback ...................................................................................................................................... 24 figure 7. remote (analog) loopback ................................................................................................................................ . 25 figure 8. ksz8081mlx power and ground connections .................................................................................................. 30 figure 9. mii sqe timing (10base - t) ................................................................................................................................ 46 figure 10. mii transmit timing (10base - t) .......................................................................................................................... 47 figure 11. mii receive timing (10base - t) ........................................................................................................................... 48 figure 12. mii transmit timing (100base - tx) ...................................................................................................................... 49 figure 13. mii receive timing (100base - tx) ....................................................................................................................... 50 figure 14. auto - negotiation fast link pulse (flp) timing .................................................................................................. 51 figure 15. mdc/mdio timing ............................................................................................................................................... 52 figure 16. power - up/reset timing ....................................................................................................................................... 53 figure 17. recommended reset circuit ............................................................................................................................... 54 figure 18. recommended reset circuit for interfacing with cpu/fpga reset output ...................................................... 54 figure 19. reference circuits for led strapping pins ......................................................................................................... 55 figure 20. 25mhz crystal/oscillator reference clock connection ...................................................................................... 56 figure 21. typical magnetic interface circuit ........................................................................................................................ 57 downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 7 revision 1.3 list of tables table 1. mii signal definition .............................................................................................................................................. 17 table 2. mii signal connection for mii back - to - back mode (100base - tx copper repeater) ........................................... 20 table 3. mii management frame format for the ksz8081mlx ........................................................................................ 21 table 4. mdi/mdi - x pin definition ...................................................................................................................................... 22 table 5. nand tree test pin order for ksz8081mlx ...................................................................................................... 27 table 6. ksz8081 power pin description ........................................................................................................................... 30 table 7. typical current/power consumption (vdda_3.3 = 3.3v, vddio = 3.3v) ........................................................... 31 table 8. typical current/power consu mption (vdda_3.3 = 3.3v, vddio = 2.5v) ........................................................... 31 table 9. typical current/power consumption (vdda_3.3 = 3.3v, vddio = 1.8v) ........................................................... 32 table 10. mii sqe timing (10base - t) parameters .............................................................................................................. 46 table 11. mii transmit timing (10base - t) parameters ....................................................................................................... 47 table 12. mii receive timing (10base - t) parameters ........................................................................................................ 48 table 13. mii transmit timing (100base - tx) parameters ................................................................................................... 49 table 14. mii receive timing (100base - tx) parameters .................................................................................................... 50 table 15. auto - negotiation fast link pulse (flp) timing parameters ................................................................................ 51 table 16. mdc/mdio timing parameters ............................................................................................................................ 52 table 17. power - up/reset timing parameters .................................................................................................................... 53 table 18. 25mhz crystal / reference clock selection criteria ............................................................................................ 56 table 19. magnetics selection criteria ................................................................................................................................ . 58 table 20. compatible single - port 10/100 magnetics ........................................................................................................... 58 downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 8 revision 1.3 pin configuration 1 ncnc txc rst# intrp / nand_tree# rext gnd rxer / iso gnd vdd_1.2 gndgnd gnd gndxo nc nc txd1 txd0 txen led1 / speed led0 / nwayen crs / config1 test/nc 2 3 8 13 14 16 17 29 30 31 32 33 34 35 36 41 42 43 44 45 46 47 48 rxptxm rxm 9 10 11 gnd 24 txd3 txd2 gnd col / config0 37 38 39 40 rxc / b-cast_off vddio nc rxdv / config2 25 26 27 28 rxd2 / phyad1 rxd1 / phyad2 rxd0 /duplex 21 22 23 mdio mdc rxd3 / phyad0 18 19 20 xi 15 txp 12 vdd_1.2nc 4 5 ncvdda_3.3 6 7 ksz8081mlx 48 - pin 7mm 7mm lqfp downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 9 revision 1.3 pin description pin number pin name type ( 2 ) pin function 1 gnd gnd ground . 2 gnd gnd ground . 3 gnd gnd ground . 4 vdd_1.2 p 1.2v core v dd (power supplied by ksz8081mlx) . decouple with 2.2f and 0.1f capacitors to ground, and join with pin 31 by power trace or plane. 5 nc ? no connect. this pin is not bonded and can be left floating. 6 nc ? no connect. this pin is not bonded and can be left floating . 7 vdda_3.3 p 3.3v analog v dd . 8 nc ? no connect. this pin is not bonded and can be left floating. 9 rxm i/o physical receive or transmit signal ( ? differential) . 10 rxp i/o physical receive or transmit signal (+ differential) . 11 txm i/o physical transmit or receive signal ( ? differential) . 12 txp i/o physical transmit or receive signal (+ differential) . 13 gnd gnd ground . 14 xo o crystal feedback for 25mhz crystal . this pin is a no connect if an oscillator or external clock source is used. 15 xi i crystal / oscillator / external clock input ( 25mhz 50ppm ). 16 rext i set phy transmit output current . connect a 6.49k resistor to ground on this pin. 17 gnd gnd ground . 18 mdio ipu/opu management interface (mii) data i/o. this pin has a weak pull - up, is open - drain, and requires an external 1.0k pull - up resistor. 19 mdc ipu management interface (mii) clock input . this clock pin is synchronous to the mdio data pin. 20 rxd3/ phyad0 ipu/o mii mode : mii receive data output[3] ( 3 ) config . mode : the pull - up/pull - down value is latched as phyaddr[0] at the de - assertion of reset. see the strappin g options section for details. 21 rxd2/ phyad1 ipd/o mii mode : mii receive data output[2] ( 3 ) config . mode : the pull - up/pull - down value is latched as phyaddr[1] at the de - assertion of reset. see the strapping options section for details. notes: 2. p = power supply. gnd = ground. i = input. o = output. i/o = bi - directional. ipu = input with internal pull - up (see electrical characteristics for value). ipd = input with internal pull - down (see electrical characteristics for v alue). ipu/o = input with internal pull - up (see electrical characteristics for value) during power - up/reset; output pin otherwise. ipd /o = input with internal pull - down (see electrical characteristics for value) during power - up/reset; output pin otherwise. ipu/opu = input with internal pull - up (see electrical characteristics for value) and output with internal pull - up (see electrical characteristics for value). 3. mii rx mode: the rxd[3:0] bits are synchronous with rxc. when rxdv is asserted, rxd[ 3:0] presents valid data to the mac. downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 10 revision 1.3 pin description (continued) pin number pin name type ( 2 ) pin function 22 rxd1/ phyad2 ipd/o mii mode : mii receive data output[1] ( 3 ) . config. mode : the pull - up/pull - down value is latched as phyaddr[2] at the de - assertion of reset. see the strapping options section for details. 23 rxd0/ duplex ipu/o mii mode : mii receive data output[0] ( 3 ) confi g. mode : the pull - up/pull - down value is latched as duplex at the de - assertion of reset. see the strapping options section for details. 24 gnd gnd ground. 25 vddio p 3.3v, 2.5v, or 1.8v digital v dd . 26 nc - no connect. this pin is not bonded and can be left floating. 27 rxdv/ config2 ipd/o mii mode : mii receive data valid output. config. mode : the pull - up/pull - down value is latched as config2 at the de - assertion of reset. see the strapping options section for details. 28 rxc/ b-cast_off ipd/o mii mode : mii receive clock output. config. mode : the pull - up/pull - down value is latched as b - cast_off at the de - assertion of reset. see the strapping options section for details. 29 rxer/ iso ipd/o mii mode : mii receive error output config. mode : the pull - up/pull - down value is latched as isolate at the de - assertion of reset see the strapping options section for details. 30 gnd gnd ground. 31 vdd_1.2 p 1.2v core v dd (power supplied by ksz8081mlx) . decouple with 0.1f capacitor to ground, and join with pin 4 by power trace or plane. 32 intrp/ nand_tree# ipu/opu interrupt output: programmable interrupt output . this pin has a weak pull - up, is open drain, and requires an external 1.0k? pull - up resistor. config. mode: the pull - up/pull - down value is latched as nand tree# at the de - assertion of reset. see the strapping options section for details. 33 txc ipd/o mii mode: mii transmit clock output . at the de - assertion of reset, this pin needs to latch in a pull - down value for normal operation. if mac side pulls this pin high, see register 16h, bit [15] for solution. it is better having an external pull - down resistor to avoid mac side pulls this pin high . 34 txen i mii mode: mii transmit enable input. downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 11 revision 1.3 pin description (continued) pin number pin name type ( 2 ) pin function 35 txd0 i mii mode : mii transmit data input[0] ( 4 ) 36 txd1 i mii mode : mii transmit data input[1] ( 4 ) 37 gnd gnd ground . 38 txd2 i mii mode : mii transmit data input[2] ( 4 ) 39 txd3 i mii m ode : mii transmit data input[3] ( 4 ) 40 col/ config0 ipd/o mii mode : mii collision detect output config . mode : the pull - up/pull - down value is latched as config0 at the de - assertion of reset. see the strapping options section for details. 41 crs/ config1 ipd/o mii mode : mii carrier sense output config . mode : the pull - up/pull - down value is latched as config1 at the de - assertion of reset. see the strapping options section for details. 42 led0/ nwayen ipu/o led output : programmable led0 output config . mode : latched as auto - negotiation enable ( register 0h, bit [ 12 ] ) at the de - assertion of reset. see the strapping options section for details. the led0 pin is programmable using register 1fh bit s [ 5:4], and is defined as follows: led mode = [00] link/activity pin state led definition no link high off link low on activity toggle blinking led mode = [01] link pin state led definition no link high off link low on led mode = [10], [11] reserved note: 4. mii tx mode: the txd[3:0] bits are synchronous with txc. when txen is asserted, txd[3: 0] presents valid data from the mac. downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 12 revision 1.3 pin description (continued) pin number pin name type (1) pin function 43 led1/ speed ipu/o led output : programmable led1 output config . mode : latched as speed ( register 0h, bit [ 13 ] ) at the de - assertion of reset. see the strapping options section for details. the led1 pin is programmable using register 1fh bit s [ 5:4], and is defined as follows: led mode = [00] speed pin state led definition 10base -t high off 100base - tx low on led mode = [01] activity pin state led definition no activity high off activity toggle blinking led mode = [10], [11] reserved 44 test/nc ipd no connect for normal operation, an external pull - up resistor for nand tree testing. 45 nc - no connect. this pin is not bonded and can be left floating. 46 nc - no connect. this pin is not bonded and can be left floating. 47 rst# ipu chip reset (active low) 48 nc - no connect. this pin is not bonded and can be left floating. strapping options the strap - in pins are latched at the de - assertion of reset. in some systems, the mac mii receive input pins may drive high/low during power - up or reset, and consequently cause the phy strap - in pins on the mii signals to be latched to unintended high/low states. in this case, external pull - ups (4.7k ? ) or pull - downs (1.0k ? ) should be added on these phy strap - in pins to ensure the intended values are strapped - in correctly. pin number pin name type ( 5 ) pin function 22 21 20 phyad2 phyad1 phyad0 ipd/o ipd/o ipu/o the phy address is latched at de - assertion of reset and is configurable to any value from 0 to 7. the default phy address is 00001. phy address 00000 is enabled only if the b -cast_of f strapping pin is pulled high. phy address bit s [4:3] are set to 00 by default. 27 41 40 config2 config1 config0 ipd/o ipd/o ipd/o the config[2:0] strap - in pins are latched at the de - assertion of reset. config[2:0] mode 000 mii (default) 110 mii back - to - back 001 C 101, 111 reserved C not used note: 5. ipu/o = input with internal pull - up (see electrical characteristics for value) during power - up/reset; output pin otherwise. ipd/o = input with internal pull - down (see electrical characteristics for value) during power - up/reset; output pin otherwise. ipu/opu = input with internal pull - up (see electrical characteristics for value) and output with internal pull - up (see electrical characteristics for value). downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 13 revision 1.3 strapping options (continued) pin number pin name type ( 5 ) pin function 29 iso ipd/o isolate mode : pull- up = enable pull- down (default) = disable at the de - assertion of reset, this pin value is latched into register 0h, bit [10]. 43 speed ipu/o speed mode : pull- up (default) = 100mbps pull- down = 10mbps at the de - assertion of reset, this pin value is latched into register 0h, bit [13] as the speed select, and also is latched into register 4h (auto - negotiation advertisement) as the speed capability support. 23 duplex ipu/o duplex mode : pull- up (default) = half -d uplex pull- down = full - duplex at the de - assertion of reset, this pin value is latched into register 0h, bit [8]. 42 nwayen ipu/o nway auto - negotiation enable : pull- up (default) = enable auto -n egotiation pull- down = disable auto - negotiation at the de - assertion of reset, this pin value is latched into register 0h, bit [12]. 28 b-cast_off ipd/o broadcast off C for phy address 0 : pull- up = phy address 0 is set as an unique phy address pull- down (default) = phy address 0 is set as a broadcast phy address at the de - assertion of reset, this pin value is latched by the chip. 32 nand_tree# ipu/opu nand tree mode : pull- up (default) = disable pull- down = enable at the de - assertion of reset, this pin value is latched by the chip. downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 14 revision 1.3 functional description: 10base- t/100base - tx transceiver the ksz8081mlx is an integrated single 3.3v supply fast ethernet transceiver . it is fully compliant with the ieee 802.3 specification, and reduces board cost and simplifies board layout by using on - chip termination resistors for the two differential pairs and by integrating the regulator to supply the 1.2v core. on the copper media side, the ksz8081mlx supports 10base - t and 100base - tx for transmission and reception of data over a standard cat - 5 unshielded twisted pair (utp) cable, and hp auto mdi/mdi - x for reliable detection of and correction for straight - through and crossover cables. on the mac processor side, the ksz8081mlx offers the media independent interface (mii) for di rect connection with mii compliant ethernet mac processors and switches. the mii management bus option gives the mac processor complete access to the ksz8081mlx control and status registers. additionally, an interrupt pin eliminates the need for the processor to poll for phy status change. 100base - tx transmit the 100base - tx transmit function performs parallel - to - serial conversion, 4b/5b encoding, scrambling, nrz - to - nrzi conversion, and mlt3 encoding and transmission. the circuitry starts with a parallel - to - serial conversion, which converts the mii data from the mac into a 125mhz serial bit stream. the data and control stream is then converted into 4b/5b coding and followed by a scrambler. the serialized data is further converted from nrz - to -n rzi format, and then transmitted in mlt3 current output. the output current is s et by an external 6.49k 1% resistor for the 1:1 transformer ratio. the output signal has a typical rise/fall time of 4ns and complies with the a nsi tp - pmd standard regarding amplitude balance, overshoot, and timing jitter. the wave - shaped 10base - t output is also incorporated into the 100base - tx transmitter. 100base - tx receive the 100base - tx receiver function performs adaptive equalization, dc restoration, mlt3 - to - nrzi conversion, data and clock recovery, nrzi - to - nrz conversion, de - scrambling, 4b/5b decoding, and serial - to - parallel conversion. the receiving side starts with the equalization filter to compensate for inter - symbol interference (isi) over the twisted pair cable. because the amplitude loss and phase distortion is a function of the cable length, the equaliz er must adjust its characteristics to optimize performance. in this design, the variable equalizer makes an ini tial estimation based on comparisons of incoming signal strength against some known cable characteristics, then tunes itself for optimization. this is an ongoing process and self - adjusts against environmental changes such as temperature variations. next, the equalized signal goes through a dc - restoration and data - conversion block. the dc - restoration circuit compensates for the effect of baseline wander and improves the dynamic range. the differential data - conversion circuit converts mlt3 format back to nrzi. the slicing threshold is also adaptive. the clock -r ecovery circuit extracts the 125mhz clock from the edges of the nrzi signal. this recov ered clock is then used to convert the nrzi signal into nrz format. this signal is sent through the de - scrambler, then the 4b/5b decoder. finally, the nrz serial data is converted to mii format and provided as the input data to the mac. scrambler/de - scrambler (100base - tx only) the scrambler spreads the power spectrum of the transmitted signal to reduce electromagnetic int erference (emi) and baseline wander. the de - scramb ler recovers the scrambled signal. 10base - t transmit the 10base - t drivers are incorporated with the 100base - tx drivers to allow for transmission using the same magnetic. the drivers perform internal wave - shaping and pre - emphasis, and output 10base - t signal s with typical amplitude of 2.5v peak. the 10base - t signals have harmonic contents that are at least 27db below the fundamental frequency when driven by an all - ones manchester - encoded signal. downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 15 revision 1.3 10base - t receive on the receive side, input buffer and level detecting squelch circuits are us ed. a differential input receiver circuit and a phase - locked loop (pll) performs the decoding function. the manchester - encoded data stream is separated into clock signal and nrz data. a squelch circuit rejects signals with levels less than 400mv , or with short pulse widths , to prevent noise at the rxp and rxm inputs from falsely triggering the decoder. when t he input exceeds the squelch limit, the pll locks onto the incoming signal and the ksz8081mlx decodes a data frame. the receive clock is kept active during idle periods between data reception s. sqe and jabber function (10base - t only) in 10base - t operation, a short pulse is put out on the col pin after each frame is transmitted. this sqe test is needed to test the 10base - t transmit/receive path. if transmit enable (txen) is high for more than 20ms ( jabbering), the 10base - t transmitter is disabled and col is asserted high. if txen is then driven low for m ore than 250ms, the 10base - t transmitter is re - enabled and col is de - ass erted (returns to low). pll clock synthesizer the ksz8081mlx generates all internal clocks and all external clocks for sys tem timing from an external 25mhz crystal, oscillator, or reference clock. auto - negotiation the ksz8081mlx conforms to the auto - negoti ation protocol, defined in clause 28 of the ieee 802.3 specification. auto - negotiation allows unshielded t wisted p air (utp) link partners to select the highest common mode of operation. during auto - negotiation, link partners advertise capabilities across the utp link to each other and then compare their own capabilities with those they received from their link partners. the highest speed and duplex setting that is common to the two link partners is selected as the mode of operation. the following list shows the speed and duplex operation mode from highest to lowest priorit y. ? priority 1: 100base - tx, full - duplex ? priority 2: 100base - tx, half - duplex ? priority 3: 10base - t, full - duplex ? priority 4: 10base - t, half - duplex if auto - negotiation is not supported or the ksz8081mlx link partner is forced to bypass auto - negotiation, then the ksz8081mlx sets its operating mode by observing the signal at its receiver. this i s known as parallel detection, and allows the ksz8081mlx to establish a link by listening for a fixed si gnal protocol in the absence of the auto - negotiation advertisement protocol. auto - negotiation is enabled by either hardware pin strapping (nwayen, pin 42) or software ( register 0h, bit [12]). by default, auto - negotiation is enabled after power - up or hardware reset. after that, auto - negotiation can be enabled or disabled by register 0h, bit [12]. if auto - negotiation is disabled, the speed is set by register 0h, bit [13], and the duplex is set by register 0h, bit [8]. the auto - negotiation link - up process is shown in figure 1 . downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 16 revision 1.3 figure 1 . auto - negotiation flow chart downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 17 revision 1.3 mii interface the media independent interface (mii) is compliant with the ieee 802.3 specification. it provides a common interface between mii phys and macs, and has the following key characteristics: ? pin count is 15 pins (6 pins for data transmission, 7 pins for data reception, and 2 pins for carrier and collision indication). ? 10mbps and 100mbps data rates are supported at both half - and full - duplex. ? data transmission and reception are independent and belong to separate signal groups. ? transmit data and receive data are each 4 bits wide, a nibble. by default, the ksz8081mlx is configured to mii mode after it is powered up or hardware reset with the following: ? a 25mhz crystal connected to xi, xo ( pin s 15, 14), or an external 25mhz clock source (oscillator) connected to xi. ? the config[2:0] strapping pins ( pin s 27, 41, 40) set to 000 (default setting). mii signal definition table 1 describes the mii signals. refer to clause 22 of the ieee 802.3 specification for detail ed information. table 1 . mii signal definition mii signal name direction (with respect to phy, ksz8081mlx signal) direction (with respect to mac) description txc output input transmit clock (2.5mhz for 10mbps; 25mhz for 100mbps) txen input output transmit enable txd[3:0] input output transmit data[3:0] rxc output input receive clock (2.5mhz for 10mbps; 25mhz for 100mbps) rxdv output input receive data valid rxd[3:0] output input receive data[3:0] rxer output input, or (not required) receive error crs output input carrier sense col output input collision detection transmit clock (txc) txc is sourced by the phy. it is a continuous clock that provides the timing reference for t xen and txd[3:0]. txc is 2.5mhz for 10mbps operation and 25mhz for 100mbps operation. transmit enable (txen) txen indicates that the mac is presenting nibbles on txd[3:0] for transmission. it i s asserted synchronously with the first nibble of the preamble and remains asserted while all nibbles to be transmitted are presented on the mii. it is negated before the first txc following the final nibble of a frame. txen transitions synchronously with respect to txc. downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 18 revision 1.3 transmit data[3:0] (txd[3:0]) when txen is asserted, txd[3:0] are the data nibbles accepted by the phy for transmission. txd[3:0] is 00 to indicate idle when txen is de - asserted. txd[3:0] transitions synchronously with respect to txc. receive clock (rxc) rxc provides the timing reference for rxdv, rxd[3:0], and rxer. in 10mbps mode, rxc is recovered from the line while the carrier is active. rxc i s derived from the phys reference clock w hen the line is idle or the link is down. in 100mbps mode, rxc is continuously recovered from the line. if the link is down, rxc is derived f rom the phys reference clock. rxc is 2.5mhz for 10mbps operation and 25mhz for 100mbps operation. receive data val id (rxdv) rxdv is driven by the phy to indicate that the phy is presenting recovered and decoded nibb les on rxd[3:0]. in 10mbps mode, rxdv is asserted with the first nibble of the start - of - frame delimiter (sfd), 5d, and remains asserted until the end of the frame. in 100mbps mode, rxdv is asserted from the first nibble of the preamble to the last nibble of the fra me. rxdv transitions synchronously with respect to rxc. receive data[3:0] (rxd[3:0]) rxd[3:0] transitions synchronously with respect to rxc. for each clock period in which rxdv is asserted, rxd[3:0] transfers a nibble of recovered data from the phy. receive error (rxer) rxer is asserted for one or more rxc periods to indicate that a symbol error (for example, a c oding error that a phy can detect that may otherwise be undetectable by the mac sub - layer) was detected somewhere in the frame being transferred from the phy. rxer transitions synchronously with respect to rxc. carrier sense (crs) crs is asserted and de - asserted as follows: in 10mbps mode, crs assertion is based on the reception of valid preambles. crs de - assertion is based on the reception of an end - of - frame (eof) marker. in 100mbps mode, crs is asserted when a start - of - stream delimiter or /j/k symbol pair is detected. crs is de - asserted wh en an end - of - stream delimiter or /t/r symbol pair is detected. additionally, the pma layer de - asserts crs if idle symbols are received without /t/r. collision (col) col is asserted in half - duplex mode whenever the transmitter and receiver are simultaneously active on the line. this inform s the mac that a collision has occurred during its transmission to the phy. col transitions asynchronously with respect to txc and rxc. mii signal diagram the ksz8081mlx mii pin connections to the mac are shown in figure 2 . downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 19 revision 1.3 figure 2 . ksz8081mlx mii interface downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 20 revision 1.3 back -to- back mode C 100mbps copper repeater two ksz8081mlx devices can be connect ed back - to - back to form a 100base - tx to 100base - tx copper repeater. figure 3 . ksz8081mlx to ksz8081mlx back -to- back copper repeater mii back - to - back mode in mii back - to - back mode, a ksz8081mlx interfaces with another ksz8081mlx to provide a complete 100mbps copper repeater solution. t he ksz8081mlx devices are configured to mii back - to - back mode after power - up or reset with the following: strapping pin config[2:0] ( pin s 27, 41, 40) set to 110 a common 25mhz reference clock connected to xi ( pin 15) of both ksz8081mlx devices mii signals connected as shown in table 2 . table 2 . mii signal connection for mii back - to - back mode (100base - tx copper repeater) ksz8081mlx (100base - tx copper) [device 1] ksz8081mlx (100base - tx copper) [device 2] pin name pin number pin type pin name pin num ber pin type rxdv 27 output txen 34 input rxd3 20 output txd3 39 input rxd2 21 output txd2 38 input rxd1 22 output txd1 36 input rxd0 23 output txd0 35 input txen 34 input rxdv 27 output txd3 39 input rxd3 20 output txd2 38 input rxd2 21 output txd1 36 input rxd1 22 output txd0 35 input rxd0 23 output downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 21 revision 1.3 mii management (miim) interface the ksz8081mlx supports the ieee 802.3 mii management interface, also known as the management data input/output (mdio) interface. this interface allows an upper - layer device , such as a mac processor, to monitor and control the state of the ksz8081mlx. an external device with miim capability is used to read the phy s tatus and/or configure the phy settings. more details about the miim interface can be found in clause 22.2.4 of the ieee 802.3 specification. the miim interface consists of the following: ? a physical connection that incorporates the clock line (mdc) and the data line (mdio). ? a specific protocol that operates across the physical connection mentioned earlier, which allows the external controller to communicate with one or more phy devices. ? a set of 16 - bit mdio registers. supported register s [0:8] are standard registers, and their functions are defined in the ieee 802.3 specification. the additional registers are provided for expanded functionality. see the register map section for details. as the default, the ksz8081mlx supports unique phy addresses 1 to 7, and broadcast phy address 0. the latter is defined in the ieee 802.3 specification, and can be used to read/write to a single ksz8081mlx device, or w rite to multiple ksz8081mlx devices simultaneously. phy address 0 can optionally be disabled as the broadcast address by either hardware pin strapping (b - cast_off, pin 28) or software ( register 16h, bit [9]), and assigned as a unique phy address. the phyad[2:0] strapping pins are used to assign a unique phy address between 0 and 7 to each ksz 8081mlx device. the miim interface can operates up to a maximum clock speed of 10mhz mac clock. table 3 shows the mii management frame format for the ksz8081mlx. table 3 . mii management frame format for the ksz8081mlx preamble start of frame read/write op code phy address bits [4:0] reg address bits [4:0] ta data bits [15:0] idle read 32 1s 01 10 00aaa rrrrr z0 dddddddd_dddddddd z write 32 1s 01 01 00aaa rrrrr 10 dddddddd_dddddddd z interrupt (intrp) intrp ( pin 32) is an optional interrupt signal that is used to inform the external c ontroller that there has been a status update to the ksz8081mlx phy register . bits [15:8] of register 1bh are the interrupt control bits to enable and disable the conditions for asserting the intrp signal. bits [7:0] of register 1bh are the interrupt status bits to indicate which interrupt conditions have occurred. the interrupt status bits are cleared after reading register 1bh. bit [9] of register 1fh sets the interrupt level to active high or active low. the default is active low. the mii management bus option gives the mac processor complete access to the ksz8081mlx control and status registers. additionally, an interrupt pin eliminates the need for the processor to poll the phy for status change. hp auto mdi/mdi-x hp auto mdi/mdi - x configuration eliminates the need to decide whether to use a straight cable or a crossover cable between the ksz8081mlx and its link partner. this feature allows the ksz8081mlx to use eit her type of cable to connect with a link partner that is in either mdi or mdi - x mode. the auto - sense function detects transmit and receive pairs from the link partner and assigns transmit and receive pairs of the ksz8081mlx accordingly. hp auto mdi/mdi - x is enabled by default. it is disabled by writing a 1 to register 1fh, bit [13]. mdi and mdi - x mode is selected by register 1fh, bit [14] if hp auto mdi/mdi - x is disa bled. an isolation transformer with symmetrical transmit and receive data paths is recomm ended to support auto mdi/mdi - x. downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 22 revision 1.3 table 4 shows how the ieee 802.3 standard defines mdi and mdi - x. table 4 . mdi/mdi - x pin definition mdi mdi -x rj - 45 pin signal rj - 45 pin signal 1 tx+ 1 rx+ 2 tx ? 2 rx ? 3 rx+ 3 tx+ 6 rx ? 6 tx ? straight cable a straight cable connects an mdi device to an mdi - x device, or an mdi - x device to an mdi device. figure 4 shows a typical straight cable connection between a nic card (mdi device) and a switch or hub (mdi - x device). figure 4 . typical straight cable connection downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 23 revision 1.3 crossover cable a crossover cable connects an mdi device to another mdi device, or an mdi - x device to another mdi - x device. figure 5 shows a typical crossover cable connection between two switches or hubs (two mdi - x devices). figure 5 . typical crossover cable connection downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 24 revision 1.3 loopback mode the ksz8081mlx supports the following loopback operations to verify analog and/or digital da ta paths. ? loca l (digital) loopback ? remote (analog) loopback local (digital) loopback this loopback mode checks the mii transmit and receive data paths between the ksz8081mlx and the external mac, and is supported for both speeds (10/100mbps) at full - duplex. the loopback data path is shown in figure 6 . 1. the mii mac transmits frames to the ksz8081mlx. 2. frames are wrapped around inside the ksz8081mlx. 3. the ksz8081mlx transmits frames back to the mii mac. figure 6 . lo cal (digital) loopback the following programming action and register settings are used for local loopback mode. for 10/100 mbps loopback, set register 0h, bit [14] = 1 // enable local loopback mode bit [13] = 0/1 // select 10mbps/100mbps speed bit [12] = 0 // disable auto - negotiation bit [8] = 1 // select full - duplex mode downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 25 revision 1.3 remote (analog) loopback this loopback mode checks the line (differential pairs, transformer, rj - 45 connector, ethernet cable) transmit and receiv e data paths between the ksz8081mlx and its link partner . it is s upported for 100base - tx full - duplex mode only. the loopback data path is shown in figure 7 . 1. the fast ethernet (100base - tx) phy link partner transmits frames to the ksz8081mlx . 2. frames are wrapped around inside the ksz8081mlx . 3. the ksz8081mlx transmits frames back to the fast ethernet (100base - tx) phy link partner. figure 7 . remote (analog) loopback the following programming steps and register settings are used for remote l oopback mode: 1. set register 0h, bits [13] = 1 // select 100mbps speed bit [12] = 0 // disable auto - negotiation bit [8] = 1 // select full - duplex mode or just auto - negotiate and link up at 100base - tx full - duplex mode with the link partner 2. set register 1fh, bit [2] = 1 // enable remote loopback mode downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 26 revision 1.3 linkmd ? cable diagnostic the linkmd function uses time - domain reflectometry (tdr) to analyze the cabling plant for common cabling problems . these include open circuits, short circuits, and impedance mismatches. linkmd works by sending a pulse of known amplitude and duration down the mdi or mdi - x pair, then analyzing the shape of the reflected signal to determine the type of fault . the time duration for the reflected signal to return provides the approximate distance to the cabling fault. the linkmd function processes this tdr information and presents it as a numerical value that can be translated to a cable distance. linkmd is initiated by accessing register 1dh, the linkmd control/status register, in conjunction with register 1fh, the phy control 2 register. the latter register is used to disable auto mdi/ mdi - x and to select either mdi or mdi - x as the cable differential pair for testing. usage the following is a sample procedure for using linkmd with registers 1dh and 1fh: 3. disable auto mdi/mdi - x by wr iting a 1 to register 1fh, bit [ 13 ]. 4. start cable diagnostic test by writing a 1 to register 1dh, bit [ 15 ]. this enable bit is self - clearing. 5. wait (poll) for register 1dh , bit [ 15 ] to return a 0, and indicating cable diagnostic test is completed. 6. read cable diagnostic test results in register 1dh , bits [ 14 : 13 ]. the results are as follows: 00 = normal condition (valid test) 01 = open condition detected in cable (valid test) 10 = short condition detected in cable (valid test) 11 = cable diagnostic test failed (invalid test) the 11 case, invalid test, occurs when the device is unable to shut down the link partner. in this instance, the test is not run, since it would be impossible for the device to determine if the detected signal is a reflection of the signal generated or a signal from another source. 7. get distance to fault by concatenating register 1dh, bits [ 8:0 ] and multiplying the result by a constant of 0. 38 . the distance to the cable fault can be determined by the following formula: d (distance to cable fault) = 0.38 x (register 1 d h, bits [8:0]) d (distance to cable fault) is expressed in meters. concatenated value of registers 1dh bit s [8 :0] should be converted to decimal before multiplying by 0. 38 . the constant (0. 38 ) may be calibrated for different cabling conditions, including cables with a velocity of propagation that varies significantly from the norm. downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 27 revision 1.3 nand tree support the ksz8081mlx provides parametric nand tree support for fault detection bet ween chip i/os and board. the nand tree is a chain of nested nand gates in which each ksz8081mlx digital i/o (nand tree input) pin i s an input to one nand gate along the chain. at the end of the chain, the crs/config1 pin provides the output for t he nested nand gates. the nand tree test process includes: ? enabling nand tree mode ? pulling all nand tree input pins high ? driving each nand tree input pin low, sequentially, according to the nand tree pin order ? checking the nand tree output to make sure there is a toggle high - to - low or low - to - high for each nand tree input driven low table 5 lists the nand tree pin order. table 5 . nand tree test pin order for ksz8081mlx pin number pin name nand tree description 18 mdio input 19 mdc input 20 rxd3 input 21 rxd2 input 22 rxd1 input 23 rxd0 input 27 rxdv input 28 rxc input 29 rxer input 32 intrp input 33 txc input 34 txen input 35 txd0 input 36 txd1 input 38 txd2 input 39 txd3 input 42 led0 input 43 led1 input 40 col input 41 crs output downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 28 revision 1.3 nand tree i/o testing use the following procedure to check for faults on the ksz8081mlx digital i/o pin connect ions to the board: 1. enable nand tree mode using either a hardware strap - in pin (nand_tree#, pin 32) or software ( register 16h, bit [5]). pin 44 test/nc has to use a pull - up resistor for normal nand tree testing. 2. use board logic to drive all ksz8081mlx nand tree input pins high. 3. use board logic to drive each nand tree input pin, in ksz8081mlx nand tree pin order, as foll ows: a. toggle the first pin (mdio) from high to low, and verify that the cr s/config1 pin switches from high to low to indicate that the first pin is connected properly. b. leave the first pin (mdio) low. c. toggle the second pin (mdc) from high to low, and verify that the crs/config1 pin switches from low to high to indicate that the second pin is connected properly. d. leave the first pin (mdio) and the second pin (mdc) low. e. toggle the third pin (rxd3) from high to low, and verify that the crs/co nfig1 pin switches from high to low to indicate that the third pin is connected properly. f. continue with this sequence until all ksz8081mlx nand tree input pins have been toggled. each ksz8081mlx nand tree input pin must cause the crs/config1 output pin to toggle h igh - to - low or low - to - high to indicate a good connection. if the crs pin fails to toggle when the ksz8081mlx i nput pin toggles from high to low, the input pin has a fault. downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 29 revision 1.3 power management the ksz8081mlx incorporates a number of power - management modes and features that provide methods to consume less energy. these are discussed in the following sections. power - saving mode power - saving mode is used to reduce the transceiver power consumption when the cable is unplugged. it is enabled by writing a 1 to register 1fh, bit [10], and is in effect when auto - negotiation mode is enabled and the cable is disconnected (no link). in this mode, the ksz8081mlx shuts down all transceiver blocks, except for the transmitter, energy detect, a nd pll circuits. by default, power - saving mode is disabled after power - up. energy - detect power - down mode energy - detect power - down (edpd) mode is used to further reduce transceiver power consumption when the cable is unplugged. it is enabled by writing a 0 to register 18h, bit [11], and is in effect when auto - negotiation mode is enabled and the cable is disconnected (no link). edpd mode works with the pll off (set by writing a 1 to register 10h, bit [4] to automatically turn the pll off in edpd mode) to turn off all ksz8081mlx transceiver blocks, except for the transmitter and energy - detect circuits. power can be reduced further by extending the time interval between transmissions of link puls es to c heck for the presence of a link partner. the periodic transmission of link pulses is needed to ensure two link par tners in the same low - power state, with auto mdi/mdi - x disabled, can wake up when the cable is connected between them. by default, energy - dete ct power - down mode is disabled after power - up. power - down mode power - down mode is used to power down the ksz8081mlx device when it is not in use after power - up. it is enabled by writing a 1 to register 0h, bit [11]. in this mode, the ksz8081mlx disables all internal functions except the mii management interface. the ksz8081mlx exits (disables) power - down mode after register 0h, bit [11] is set back to 0. slow - oscillator mode slow - oscillator mode is used to disconnect the input reference crystal/clock on xi ( pin 15) and select the on - chip slow oscillator when the ksz8081mlx device is not in use after power - up. it is enabled by writing a 1 to register 11h, bit [5]. slow - oscillator mode works in conjunction with power - down mode to put the ksz8081mlx device in the lowest power state with all internal functions disabled except the mii management interface. t o properly exit this mode and return to normal phy operation, use the following programming sequence: 1. disable slow - oscillator mode by writing a 0 to register 11h, bit [5]. 2. disable power - down mode by writing a 0 to register 0h, bit [11]. 3. initiate software reset by writing a 1 to register 0h, bit [15]. downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 30 revision 1.3 reference circuit for power and ground connections the ksz8081mlx is a single 3.3v supply device with a built - in regulator to supply the 1.2v core. the power and ground connections are shown in figure 8 and table 6 for 3.3v vddio. figure 8 . ksz8081mlx power and ground connections table 6 . ksz8081 power pin description power pin pin number description vdd_1.2 4 connect with pin 31 by power trace or plane. decouple with 2.2 f and 0.1 f capacitors to ground. vdda_3.3 7 connect to boards 3.3v supply through a ferrite bead. decouple with 22 f and 0.1 f capacitors to ground. vddio 25 connect to boards 3.3v supply for 3.3v vddio. decouple with 22 f and 0.1 f capacitors to ground. vdd_1.2 31 connect with pin 4 by power trace or plane. decouple with 0.1 f capacitor to ground. downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 31 revision 1.3 typical current/power consumption table 7 , table 8 , and table 9 show typical values for current consumption by the transceiver (vdd a_3.3) and digital i/o (vddio) power pins and typical values for power consumption by the ksz8081mlx device for the indi cated nominal operating voltages. these current and power consumption values include the transmit driver cur rent and on - chip regulator current for the 1.2v core. table 7 . typical current/power consumption (vdda_3.3 = 3.3v, vddio = 3.3v) transceiver (3.3v), digital i/os (3.3v) condition 3.3v transceiver (vdda_3.3) 3.3v digital i/os (vddio) total chip power ma ma mw 100base - tx link - up (no traffic) 34 12 152 100base - tx full - duplex @ 100% utilization 34 13 155 10base - t link - up (no traffic) 14 11 82.5 10base - t full - duplex @ 100% utilization 30 11 135 power - saving mode (reg. 1fh, bit [10] = 1) 14 10 79.2 edpd mode (reg. 18h, bit [11] = 0) 10 10 66.0 edpd mode (reg. 18h, bit [11] = 0) and pll off (reg. 10h, bit [4] = 1) 3.77 1.54 17.5 software power - down mode (reg. 0h, bit [11] =1) 2.59 1.51 13.5 software power - down mode (reg. 0h, bit [11] =1) and slow - oscillator mode (reg. 11h, bit [5] =1) 1.36 0.45 5.97 table 8 . typical current/power consumption (vdda_3.3 = 3.3v, vddio = 2.5v) transceiver (3.3v), digital i/os (2.5v) condition 3.3v transceiver (vdda_3.3) 2.5v digital i/os (vddio) total chip power ma ma mw 100base - tx link - up (no traffic) 34 11 140 100base - tx full - duplex @ 100% utilization 34 12 142 10base - t link - up (no traffic) 15 10 74.5 10base - t full - duplex @ 100% utilization 27 10 114 power - saving mode (reg. 1fh, bit [10] = 1) 15 10 74.5 edpd mode (reg. 18h, bit [11] = 0) 11 10 61.3 edpd mode (reg. 18h, bit [11] = 0) and pll off (reg. 10h, bit [4] = 1) 3.55 1.35 15.1 software power - down mode (reg. 0h, bit [11] =1) 2.29 1.34 10.9 software power - down mode (reg. 0h, bit [11] =1) and slow - oscillator mode (reg. 11h, bit [5] =1) 1.15 0.29 4.52 downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 32 revision 1.3 table 9 . typical current/power consumption (vdda_3.3 = 3.3v, vddio = 1.8v) transceiver (3.3v), digital i/os (1.8v) condition 3.3v transceiver (vdda_3.3) 1.8v digital i/os ( vddio) total chip power ma ma mw 100base - tx link - up (no traffic) 34 11 132 100base - tx full - duplex @ 100% utilization 34 12 134 10base - t link - up (no traffic) 15 9.0 65.7 10base - t full - duplex @ 100% utilization 27 9.0 105 power - saving mode (reg. 1fh, bit [10] = 1) 15 9.0 65.7 edpd mode (reg. 18h, bit [11] = 0) 11 9.0 52.5 edpd mode (reg. 18h, bit [11] = 0) and pll off (reg. 10h, bit [4] = 1) 4.05 1.21 15.5 software power - down mode (reg. 0h, bit [11] =1) 2.79 1.21 11.4 software power - down mode (reg. 0h, bit [11] =1) and slow - oscillator mode (reg. 11h, bit [5] =1) 1.65 0.19 5.79 downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 33 revision 1.3 register map register number (hex) description 0h basic control 1h basic status 2h phy identifier 1 3h phy identifier 2 4h auto- negotiation advertisement 5h auto- negotiation link partner ability 6h auto- negotiation expansion 7h auto- negotiation next page 8h link partner next page ability 9h C fh reserved 10h digital reserved control 11h afe control 1 12h C 14h reserved 15h rxer counter 16h operation mode strap override 17h operation mode strap status 18h expanded control 19h C 1ah reserved 1bh interrupt control/status 1ch reserved 1dh linkmd control/status 1eh phy control 1 1fh phy control 2 downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 34 revision 1.3 register description address name description mode (6) default register 0h C basic control 0.15 reset 1 = software reset 0 = normal operation this bit is self - cleared after a 1 is written to it. rw/sc 0 0.14 loopback 1 = loopback mode 0 = normal operation rw 0 0.13 speed select 1 = 100mbps 0 = 10mbps this bit is ignored if auto - negotiation is enabled ( register 0.12 = 1). rw set by the speed strapping pin. see the strapping options section for details. 0.12 auto- negotiation enable 1 = enable auto - negotiation process 0 = disable auto - negotiation process if enabled, the auto - negotiation result overrides the settings in register 0.13 and 0.8. rw set by the nwayen strapping pin. see the strapping options section for details. 0.11 power - down 1 = power - down mode 0 = normal operation if software reset ( register 0.15) is used to exit power - down mode ( register 0.11 = 1), two software reset writes ( register 0.15 = 1) are required. the first write clears power - down mode; the second write resets the chip and re - latches the pin strapping pin values. rw 0 0.10 isolate 1 = electrical isolation of phy from mii 0 = normal operation rw set by the iso strapping pi n. see the strapping options section for details. 0.9 restart auto - negotiation 1 = restart auto - negotiation process 0 = normal operation. this bit is self - cleared after a 1 is written to it. rw/sc 0 0.8 duplex mode 1 = full - duplex 0 = half - duplex rw the i nverse of the duplex strapping pin value. see the strapping options section for details. 0.7 collision test 1 = enable col test 0 = disable col test rw 0 0.6:0 reserved reserved ro 000_0000 note: 6. rw = read/write. ro = read only. sc = self - cleared. lh = latch high. ll = latch low. downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 35 revision 1.3 register description (continued) address name description mode (6) default register 1h C basic status 1.15 100base - t4 1 = t4 capable 0 = not t4 capable ro 0 1.14 100base - tx full - duplex 1 = capable of 100mbps full - duplex 0 = not capable of 100mbps full - duplex ro 1 1.13 100base - tx half - duplex 1 = capable of 100mbps half - duplex 0 = not capable of 100mbps half - duplex ro 1 1.12 10base - t full - duplex 1 = capable of 10mbps full - duplex 0 = not capable of 10mbps full - duplex ro 1 1.11 10base - t half - duplex 1 = capable of 10mbps half - duplex 0 = not capable of 10mbps half - duplex ro 1 1.10:7 reserved reserved ro 000_0 1.6 no preamble 1 = preamble suppression 0 = normal preamble ro 1 1.5 auto- negotiation complete 1 = auto - negotiation process completed 0 = auto - negotiation process not completed ro 0 1.4 remote fault 1 = remote fault 0 = no remote fault ro/lh 0 1.3 auto- negotiation ability 1 = can perform auto - negotiation 0 = cannot perform auto - negotiation ro 1 1.2 link status 1 = link is up 0 = link is down ro/ll 0 1.1 jabber detect 1 = jabber detected 0 = jabber not detected (default is low) ro/lh 0 1.0 extended capability 1 = supports extended capability registers ro 1 register 2h C phy identifier 1 2.15:0 phy id number assigned to the 3rd through 18th bits of the organizationally unique identifier (oui). kendin communications oui is 0010a1 (hex) . ro 0022h register 3h C phy identifier 2 3.15:10 phy id number assigned to the 19th through 24th bits of the organizationally unique identifier (oui). kendin communications oui is 0010a1 (hex) . ro 0001_01 3.9:4 model number six- bit manufacturers model number ro 01_0110 3.3:0 revision number four - bit manufacturers revision number ro indicates silicon revision downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 36 revision 1.3 register description (continued) address name description mode (6) default register 4h C auto - negotiation advertisement 4.15 next page 1 = next page capable 0 = no next page capability rw 0 4.14 reserved reserved ro 0 4.13 remote fault 1 = remote fault supported 0 = no remote fault rw 0 4.12 reserved reserved ro 0 4.11:10 pause [00] = no pause [10] = asymmetric pause [01] = symmetric pause [11] = asymmetric and symmetric pause rw 00 4.9 100base - t4 1 = t4 capable 0 = no t4 capability ro 0 4.8 100base - tx full - duplex 1 = 100mbps full - duplex capable 0 = no 100mbps full - duplex capability rw set by the speed strapping pin. see the strapping options section for d etails. 4.7 100base - tx half - duplex 1 = 100mbps half - duplex capable 0 = no 100mbps half - duplex capability rw set by the speed strapping pin. see the strapping options section for details. 4.6 10base - t full - duplex 1 = 10mbps full - duplex capable 0 = no 10mbps full - duplex capability rw 1 4.5 10base - t half - duplex 1 = 10mbps half - duplex capable 0 = no 10mbps half - duplex capability rw 1 4.4:0 selector field [00001] = ieee 802.3 rw 0_0001 register 5h C auto - negotiation link partner ability 5.15 next page 1 = next page capable 0 = no next page capability ro 0 5.14 acknowledge 1 = link code word received from partner 0 = link code word not yet received ro 0 5.13 remote fault 1 = remote fault detected 0 = no remote fault ro 0 5.12 reserved reserved ro 0 5.11:10 pause [00] = no pause [10] = asymmetric pause [01] = symmetric pause [11] = asymmetric and symmetric pause ro 00 5.9 100base - t4 1 = t4 capable 0 = no t4 capability ro 0 5.8 100base - tx full - duplex 1 = 100mbps full - duplex capable 0 = no 100mbps full - duplex capability ro 0 downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 37 revision 1.3 register description (continued) address name description mode (6) default register 5h C auto - negotiation link partner ability 5.7 100base - tx half - duplex 1 = 100mbps half - duplex capable 0 = no 100mbps half - duplex capability ro 0 5.6 10base - t full - duplex 1 = 10mbps full - duplex capable 0 = no 10mbps full - duplex capability ro 0 5.5 10base - t half - duplex 1 = 10mbps half - duplex capable 0 = no 10mbps half - duplex capability ro 0 5.4:0 selector field [00001] = ieee 802.3 ro 0_0001 register 6h C auto - negotiation expansion 6.15:5 reserved reserved ro 0000_0000_000 6.4 parallel detection fault 1 = fault detected by parallel detection 0 = no fault detected by parallel detection ro/lh 0 6.3 link partner next page able 1 = link partner has next page capability 0 = link partner does not have next page capability ro 0 6.2 next page able 1 = local device has next page capability 0 = local device does not have next page capability ro 1 6.1 page received 1 = new page received 0 = new page not received yet ro/lh 0 6.0 link partner auto - negotiation able 1 = link partner has auto - negotiation capability 0 = link partner does not have auto - negotiation capability ro 0 register 7h C auto - negotiation next page 7.15 next page 1 = additional next pages will follow 0 = last page rw 0 7.14 reserved reserved ro 0 7.13 message page 1 = message page 0 = unformatted page rw 1 7.12 acknowledge2 1 = will comply with message 0 = cannot comply with message rw 0 7.11 toggle 1 = previous valu e of the transmitted link code word equaled logic 1 0 = logic 0 ro 0 7.10:0 message field 11 - bit wide field to encode 2048 messages rw 000_0000_0001 downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 38 revision 1.3 register description (continued) address name description mode (6) default register 8h C link partner next page ability 8.15 next page 1 = additional next pages will follow 0 = last page ro 0 8.14 acknowledge 1 = successful receipt of link word 0 = no successful receipt of link word ro 0 8.13 message page 1 = message page 0 = unformatted page ro 0 8.12 acknowledge2 1 = can act on the information 0 = cannot act on the information ro 0 8.11 toggle 1 = previous value of transmitted link code word equal to logic 0 0 = previous value of transmitted link code word equal to logic 1 ro 0 8.10:0 message field 11 - bit wide field to encode 2048 messages ro 000_0000_0000 register 10h C digital reserved control 10.15:5 reserved reserved rw 0000_0000_000 10.4 pll o ff 1 = turn pll off automatically in edpd mode 0 = keep pll on in edpd mode. see also register 18h, bit [11] for edpd mode rw 0 10.3:0 reserved reserved rw 0000 register 11h C afe control 1 11.15:6 reserved reserved rw 0000_0000_00 11.5 slow- oscillator mode enable slow- oscillator mode is used to disconnect the input reference crystal/clock on the xi pin and select the on - chip slow oscillator when the ksz8081mlx device is not in use after power - up. 1 = enable 0 = disable this bit automatic ally sets software power - down to the analog side when enabled. rw 0 11.4:0 reserved reserved rw 0_0000 register 15h C rxer counter 15.15:0 rxer counter receive error counter for symbol error frames ro/sc 0000h downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 39 revision 1.3 register description (continued) address name description mode (6) default register 16h C operation mode strap override 16.15 reserved factory mode 0 = normal operation 1 = factory test mode if txc (pin 33) la tches in a pull - up value at the de - assertion of re set, write a 0 to this bit to clear reserved factory mode. rw 0 set by the pull - up / pull - down value of txc (pin 33). 16.1 4 :11 reserved reserved rw 000_0 16.10 reserved reserved ro 0 16.9 b-cast_off override 1 = override strap - in for b - cast_off if bit is 1, phy address 0 is non - broadcast. rw 0 16.8 reserved reserved rw 0 16.7 mii b - to -b override 1 = override strap - in for mii back - to - back mode (also set bit 0 of this register to 1) rw 0 16.6 reserved reserved rw 0 16.5 nand tree override 1 = override strap - in for nand tree mode rw 0 16.4:1 reserved reserved rw 0_000 16.0 mii override 1 = override strap - in for mii mode rw 1 register 17h C operation mode strap status 17.15:13 phyad[2:0] strap - in status [000] = strap to phy address 0 [001] = strap to phy address 1 [010] = strap to phy address 2 [011] = strap to phy address 3 [100] = strap to phy address 4 [101] = strap to phy address 5 [110] = strap to phy address 6 [111] = strap to phy address 7 ro 17.12:10 reserved reserved ro 17.9 b-cast_off strap- in status 1 = strap to b -cast_off if bit is 1, phy address 0 is non - broadcast. ro 17.8 reserved reserved ro 17.7 mii b - to - b strap - in status 1 = strap to mii back - to - back mode ro 17.6 reserved reserved ro 17.5 nand tree strap - in status 1 = strap to nand tree mode ro 17.4:1 reserved reserved ro 17.0 mii strap - in status 1 = strap to mii mode ro downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 40 revision 1.3 register description (continued) address name description mode (6) default register 18h C expanded control 18.15:12 reserved reserved rw 0000 18.11 edpd disabled energy - detect power - down mode 1 = disable 0 = enable see also register 10h, bit [4] for pll off. rw 1 18.10 100base - tx latency 1 = mii output is random latency 0 = mii output is fixed latency for both settings, all bytes of received preamble are passed to the mii output. rw 0 18.9:7 reserved reserved rw 00_0 18.6 10base - t preamble restore 1 = restore received preamble to mii output 0 = remove all seven bytes of preamble before sending fr ame (starting with sfd) to mii output rw 0 18.5:0 reserved reserved rw 00_0000 register 1bh C interrupt control/status 1b.15 jabber interrupt enable 1 = enable jabber interrupt 0 = disable jabber interrupt rw 0 1b.14 receive error interrupt enable 1 = enable receive error interrupt 0 = disable receive error interrupt rw 0 1b.13 page received interrupt enable 1 = enable page received interrupt 0 = disable page received interrupt rw 0 1b.12 parallel detect fault interrupt enable 1 = enable parallel detect fault interrupt 0 = disable parallel detect fault interrupt rw 0 1b.11 link partner acknowledge interrupt enable 1 = enable link partner acknowledge interrupt 0 = di sable link partner acknowledge interrupt rw 0 1b.10 link - down interrupt enable 1= enable link - down interrupt 0 = disable link - down interrupt rw 0 1b.9 remote fault interrupt enable 1 = enable remote fault interrupt 0 = disable remote fault interrupt rw 0 1b.8 link - up interrupt enable 1 = enable link - up interrupt 0 = disable link - up interrupt rw 0 1b.7 jabber interrupt 1 = jabber occurred 0 = jabber did not occur ro/sc 0 1b.6 receive error interrupt 1 = receive error occurred 0 = receive error did not occur ro/sc 0 1b.5 page receive interrupt 1 = page receive occurred 0 = page receive did not occur ro/sc 0 downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 41 revision 1.3 register description (continued) address name description mode (6) default register 1bh C interrupt control/status (continued) 1b.4 parallel detect fault interrupt 1 = parallel detect fault occurred 0 = parallel detect fault did not occur ro/sc 0 1b.3 link partner acknowledge interrupt 1 = link partner acknowledge occurred 0 = link partner acknowledge did not occur ro/sc 0 1b.2 link - down interrupt 1 = link - down occurred 0 = link - down did not occur ro/sc 0 1b.1 remote fault interrupt 1 = remote fault occurred 0 = remote fault did not occur ro/sc 0 1b.0 link - up interrupt 1 = link - up occurred 0 = link - up did not occur ro/sc 0 register 1dh C linkmd control/status 1d.15 cable diagnostic test enable 1 = enable cab le diagnostic test. after test has completed, this bit is self - cleared. 0 = indicates cable diagnostic test (if enabled) has completed and the status information is valid for read. rw/sc 0 1d.14:13 cable diagnostic test result [00] = normal condition [01] = open condition has been detected in cable [10] = short condition has been det ected in cable [11] = cable diagnostic test has failed ro 00 1d.12 short cable indicator 1 = short cable (<10 meter) has been detected by linkmd ro 0 1d.11:9 reserved reserved rw 000 1d.8:0 cable fault counter distance to fault ro 0_0000_0000 register 1eh C phy control 1 1e.15:10 reserved reserved ro 0000_00 1e.9 enable pause (flow control) 1 = flow control capable 0 = no flow control capability ro 0 1e.8 link status 1 = link is up 0 = link is down ro 0 1e.7 polarity status 1 = polarity is reversed 0 = polarity is not reversed ro 1e.6 reserved reserved ro 0 1e.5 mdi/mdi - x state 1 = mdi -x 0 = mdi ro downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 42 revision 1.3 register description (continued) address name description mode (6) default register 1eh C phy control 1 (continued) 1e.4 energy detect 1 = presence of signal on receive differential pair 0 = no signal de tected on receive differential pair ro 0 1e.3 phy isolate 1 = phy in isolate mode 0 = phy in normal operation rw 0 1e.2:0 operation mode indication [000] = still in auto - negotiation [001] = 10base - t half - duplex [010] = 100base - tx half - duplex [011] = reserved [100] = reserved [101] = 10base - t full - duplex [110] = 100base - tx full - duplex [111] = reserved ro 000 register 1fh C phy control 2 1f.15 hp_mdix 1 = hp auto mdi/mdi - x mode 0 = micrel auto mdi/mdi - x mode rw 1 1f.14 mdi/mdi - x select when auto mdi/mdi - x is disabled, 1 = mdi - x mode transm it on rxp,rxm ( pin s 10, 9) and receive on txp, txm ( pin s 12, 11) 0 = mdi mode transm it on txp,txm ( pin s 12, 11) and receive on rxp,rxm ( pin s 10, 9) rw 0 1f.13 pair swap disable 1 = disable auto mdi/mdi -x 0 = enable auto mdi/mdi -x rw 0 1f.12 reserved reserved rw 0 1f.11 force link 1 = force link pass 0 = normal link operation this bit bypasses the control logic and allows the transmitter to send a pattern even if there is no link. rw 0 1f.10 power saving 1 = enable power saving 0 = disable power saving rw 0 1f.9 interrupt level 1 = interrupt pin active high 0 = interrupt pin active low rw 0 1f.8 enable jabber 1 = enable jabber counter 0 = disable jabber counter rw 1 1f.7:6 reserved reserved rw 00 downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 43 revision 1.3 register description (continued) address name description mode (6) default register 1fh C phy control 2 (continued) 1f.5:4 led mode [00] = led1: speed led0: link/activity [01] = led1: activity led0: link [10], [11] = reserved rw 00 1f.3 disable transmitter 1 = disable transmitter 0 = enable transmitter rw 0 1f.2 remote loopback 1 = remote (analog) loopback is enabled 0 = normal mode rw 0 1f.1 enable sqe test 1 = enable sqe test 0 = disable sqe test rw 0 1f.0 disable data scrambling 1 = disable scrambler 0 = enable scrambler rw 0 downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 44 revision 1.3 absolute maximum ratings ( 7 ) supply voltage (v in ) (v dd_1.2 ) .................................................. ? 0.5v to +1.8v (v ddio, v dda_3.3 ) ....................................... ? 0.5v to +5.0v input voltage (all inputs) .............................. ? 0.5v to +5.0v output voltage (all outputs) ......................... ? 0.5v to +5.0v lea d temperature (soldering, 10s ) ............................ 260c storage temperature (t s ) ......................... C 55c to +150c operating ratings ( 8 ) supply voltage (v ddio_3.3, v dda_3.3 ) .......................... +3.135v to +3.465v (v ddio_2.5 ) ........................................ +2.375v to +2.625v (v ddio_1.8 ) ........................................ +1.710v to +1.890v ambient temperature (t a , commercial) ...................................... 0c to +70c (t a , industrial ) ...................................... C 40c to +85c maximum junction temperature (t j maximum ) ........ 125c thermal resistance ( ja ) ......................................... 76c/w thermal resistance ( jc ) ......................................... 15c/w electrical characteristics ( 9 ) symbol parameter condition min. typ. max. units supply current (v ddio , v dda_3.3 = 3.3v) ( 10 ) i dd1_3.3v 10base -t full - duplex traffic @ 100% utilization 41 ma i dd2_3.3v 100base - tx full - duplex traffic @ 100% utilization 47 ma i dd3_3.3v edpd mode ethernet cable disconnected (reg. 18h.11 = 0) 20 ma i dd4_3.3v power - down mode software power - down (reg. 0h.11 = 1) 4 ma cmos level inputs v ih input high voltage v ddio = 3.3v 2.0 v v ddio = 2.5v 1.8 v ddio = 1.8v 1.3 v il input low voltage v ddio = 3.3v 0.8 v v ddio = 2.5v 0.7 v ddio = 1.8v 0.5 |i in | input current v in = gnd ~ vddio 10 a cmos level outputs v oh output high voltage v ddio = 3.3v 2.4 v v ddio = 2.5v 2.0 v ddio = 1.8v 1.5 v ol output low voltage v ddio = 3.3v 0.4 v v ddio = 2.5v 0.4 v ddio = 1.8v 0.3 |i oz | output tri - state leakage 10 a led outputs i led output drive current each led pin (led0, led1) 8 ma notes: 7. exceeding the absolute maximum rating can damage the device. stresses greater than the absolute m aximum rating can cause permanent damage to the device. operation of the device at these or any other conditions above those specified in the ope rating sections of this specification is not implied. maximum conditions for extended periods may affect reliability. 8. the device is not guaranteed to function outside its operating rating. 9. t a = 25c. specificatio n is for packaged product only. 10. current consumption is for the single 3.3v supply ksz8081mlx device only, and includes the tr ansmit driver current and the 1. 2v s upply voltage (v dd_1.2 ) that are supplied by the ksz8081mlx. downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 45 revision 1.3 electrical characteristics ( 9 ) (continued) symbol parameter condition min. typ. max. units all pull - up/pull - down pins (including s trapping p ins) pu internal pull - up resistance v ddio = 3.3v 30 45 73 k v ddio = 2.5v 39 61 102 v ddio = 1.8v 48 99 178 pd internal pull - down resistance v ddio = 3.3v 26 43 79 k v ddio = 2.5v 34 59 113 v ddio = 1.8v 53 99 200 100base - tx transmit (measured differentially after 1:1 transformer) v o peak differential output voltage 100 termination across differential output 0.95 1.05 v v imb output voltage imbalance 100 termination across differential output 2 % t r , t f rise/fall time 3 5 ns rise/fall time imbalance 0 0.5 ns duty cycle distortion 0.25 ns overshoot 5 % output jitter peak - to - peak 0.7 ns 10base - t transmit (measured differentially after 1:1 transformer) v p peak differential output voltage 100 termination across differential output 2.2 2.8 v jitter added peak - to - peak 3.5 ns t r , t f rise/fall time 25 ns 10base - t receive v sq squelch threshold 5mhz square wave 400 mv transmitter C drive setting v set reference voltage of i set r(i set ) = 6.49k 0.65 v 100mbps mode C industrial applications parameters clock phase delay C xi input to mii txc output xi (25mhz clock input) to mii txc (25mhz clock output) delay, referenced to rising edges of both clocks. 15 20 25 ns t llr link loss reaction (indication) time link loss detected at receive differential inputs to phy signal indication time for each of the following: 1. for led m ode 00, speed led output change s from low (100mbps) to high (10mbps, default state for link - down). 2. for led mode 01, link led output change s from low (link - up) to high (link - down). 3. intrp pin asser ts for link - down status change. 4.4 s downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 46 revision 1.3 timing diagrams mii sqe timing (10base - t) figure 9 . mii sqe timing (10base - t) table 10 . mii sqe timing (10 base - t) parameters timing parameter description min. typ. max. unit t p txc period 400 ns t wl txc pulse width low 200 ns t wh txc pulse width high 200 ns t sqe col (sqe) delay after txen de - asserted 2.2 s t sqep col (sqe) pulse duration 1.0 s downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 47 revision 1.3 mii transmit timing (10base - t) figure 10 . mii transmit timing (10base - t) table 11 . mii transmit timing (10base - t) parameters timing parameter description min. typ. max. unit t p txc period 400 ns t wl txc pulse width low 200 ns t wh txc pulse width high 200 ns t su1 txd[3:0] setup to rising edge of txc 120 ns t su2 txen setup to rising edge of txc 120 ns t hd1 txd[3:0] hold from rising edge of txc 0 ns t hd2 txen hold from rising edge of txc 0 ns t crs1 txen high to crs asserted latency 600 ns t crs2 txen low to crs de - asserted latency 1.0 s downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 48 revision 1.3 mii receive timing (10base - t) figure 11 . mii receive timing (10base - t) table 12 . mii receive timing (10base - t) parameters timing parameter description min. typ. max. unit t p rxc period 400 ns t wl rxc pulse width low 200 ns t wh rxc pulse width high 200 ns t od (rxdv, rxd[3:0], rxer) output delay from rising edge of rxc 205 ns t rlat crs to (rxdv, rxd[3:0]) latency 7.2 s downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 49 revision 1.3 mii transmit timing (100base - tx) figure 12 . mii transmit timing (100 base -tx) table 13 . mii transmit timing (100base - tx) parameters timing parameter description min. typ. max. unit t p txc period 40 ns t wl txc pulse width low 20 ns t wh txc pulse width high 20 ns t su1 txd[3:0] setup to rising edge of txc 10 ns t su2 txen setup to rising edge of txc 10 ns t hd1 txd[3:0] hold from rising edge of txc 0 ns t hd2 txen hold from rising edge of txc 0 ns t crs1 txen high to crs asserted latency 72 ns t crs2 txen low to crs de - asserted latency 72 ns downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 50 revision 1.3 mii receive timing (100base - tx) figure 13 . mii receive timing (100base -tx) table 14 . mii receive timing (100base - tx) parameters timing parameter description min. typ. max. unit t p rxc period 40 ns t wl rxc pulse width low 20 ns t wh rxc pulse width high 20 ns t od (rxdv, rxd[3:0], rxer) output delay from rising edge of rxc 16 21 25 ns t rlat crs to (rxdv, rxd[3:0] latency 170 ns downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 51 revision 1.3 auto - negotiation timing figure 14 . auto - negotiation fast link pulse (flp) timing table 15 . auto - negotiation fast link pulse (flp) timing parameters timing parameter description min. typ. max. units t btb flp burst to flp burst 8 16 24 ms t flpw flp burst width 2 ms t pw clock/data pulse width 100 ns t ctd clock pulse to data pulse 55.5 64 69.5 s t ctc clock pulse to clock pulse 111 128 139 s number of clock/data pulses per flp burst 17 33 downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 52 revision 1.3 mdc/mdio timing figure 15 . mdc/mdio timing table 16 . mdc/mdio timing parameters timing parameter description min. typ. max. unit fc mdc clock frequency 2.5 10 mhz t p mdc period 400 ns t md1 mdio (phy input) setup to rising edge of mdc 10 ns t md2 mdio (phy input) hold from rising edge of mdc 4 ns t md3 mdio (phy output) delay from rising edge of mdc 5 222 ns downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 53 revision 1.3 power - up/reset timing the ksz8081mlx reset timing requirement is summarized in figure 16 and table 17 . figure 16 . power - up/reset timing table 17 . power - up/reset timing parameters parameter description min. max. units t vr supply voltage (v ddio, v dda_3.3 ) rise time 300 s t sr stable supply voltage (v ddio, v dda_3.3 ) to reset high 10 ms t cs configuration setup time 5 ns t ch configuration hold time 5 ns t rc reset to strap - in pin output 6 ns the supply voltage ( v ddio and v dda_3.3 ) power - up waveform should be monotonic . t he 300 s minimum rise time is from 10% to 90%. for warm reset, the reset (rst#) pin should be asserted low for a minimu m of 500 s. the strap - in pin values are read and updated at the de - assertion of reset. after the de - assertion of reset, wait a minimum of 100 s before starting programming on the miim (mdc/mdio) interface. downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 54 revision 1.3 reset circuit figure 17 shows a reset circuit recommended for powering up the ksz8081mlx if reset is triggered by the p ower supply. figure 17 . recommended reset circuit figure 18 s hows a reset circuit recommended for applications where reset is driven by an other device (for example, the cpu or an fpga). the reset out rst_out_n from cpu/fpga provides the warm reset after power up reset . d2 is used if using different vddio between the switch and cpu/fpga, otherwise, the diff erent vddio will fight each other. if different vddio have to use in a special case, a low vf (<0.3v) diode is required (for exampl e, v ishay s bat54, mss1p2l and so on), or a level shifter device can be used too. if ethernet device and cpu/fpga use same vddio voltage, d2 can be removed to connect both devices directly. usually, eth ernet device and cpu/fpga should use same vddio voltage. figure 18 . recommended reset circuit for i nterfacing with cpu/fpga reset output downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 55 revision 1.3 reference circuits ? led strap-in pins the pull - up, float, and pull - down reference circuits for the led1/speed and led0/nwayen strapping pins are shown in figure 19 for 3.3v and 2.5v vddio. figure 19 . reference circuits for led strapping pins for 1.8v vddio, led indication support is not recommended due to the low voltage. without the led i ndicator, the speed and nwayen strapping pins are functional with a 4.7k pull - up to 1.8v vddio or float for a value of 1, and with 1.0k pull - down to ground for a value of 0. note: if using rj45 jacks with integrated leds and 1.8v vddio, a lev el shifting is required from led 3.3v to 1.8v. for example, use a bipolar transistor or a level shift device. downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 56 revision 1.3 reference clock ? connection and selection a crystal or external clock source, such as an oscillator, is used to pro vide the reference clock for the ksz8081mlx. for the ksz8081mlx in all operating modes, the reference clock is 25mhz. the referenc e clock connections to xi ( pin 15) and xo ( pin 14), and the reference clock selection criteria, are provided in figure 20 and table 18 . figure 20 . 25mhz crystal/oscillator reference clock connection table 18 . 25mhz crystal / reference clock selection criteria characteristics value units frequency 25 mhz frequency tolerance (max imum ) ( 11 ) 50 p pm crystal series resistance (typical ) 40 crystal load capacitance (typical ) 16 pf note: 11. 60ppm for overtemperature crystal. downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 57 revision 1.3 magnetic ? connection and selection a 1:1 isolation transformer is required at the line interface. use one with integrated comm on - mode chokes for designs exceeding fcc requirements. the ksz8081mlx design incorporates voltage - mode transmit drivers and on - chip terminations. with the voltage - mode implementation, the transmit drivers supply the common - mode voltages to the two differential pairs. therefore, the two transformer center tap pins on the ksz8081mlx side should not be connected to any power supply source on the board; instead , the center tap pins should be separated from one another and connected through separate 0.1f common - mode capacitors to ground. separation is required because the common - mode voltage is different between transmitting and receiving differential pairs . figure 21 shows the typical magnetic interface circuit for the ksz8081mlx. figure 21 . typical magnetic interface circuit downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 58 revision 1.3 table 19 lists recommended magnetic characteristics. table 19 . magnetics selection criteria parameter value test condition turns ratio 1 ct : 1 ct open - circuit inductance (min.) 350 h 100mv, 100khz, 8ma insertion loss (typ.) C 1.1db 100khz to 100mhz hipot (min.) 1500vrms table 20 is a list of compatible single - port magnetics with separated transformer center tap pins on the phy chip side that can be used with the ksz80 81mlx. table 20 . compatible single - port 10/100 magnetics manufacturer part number temperature range magnetic + rj - 45 bel fuse s558 - 5999 - u7 0c to 70c no bel fuse si- 46001 -f 0c to 70c yes bel fuse si- 50170 -f 0c to 70c yes delta lf8505 0c to 70c no halo hfj11 - 2450e 0c to 70c yes halo tg110 - e055n5 C 40c to 85c no lankom lf - h41s -1 0c to 70c no pulse h1102 0c to 70c no pulse h1260 0c to 70c no pulse hx1188 C 40c to 85c no pulse j00 - 0014 0c to 70c yes pulse jx0011d21nl C 40c to 85c yes tdk tla - 6t718a 0c to 70c yes transpower hb726 0c to 70c no wurth/midcom 000 - 7090 - 37r - lf1 C 40c to 85c no downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 59 revision 1.3 package information and recommended land pattern ( 12 ) 48 -pin 7mm 7mm lqfp ( mm ) note: 12. package information is correct as of the publication date. for updates and most current i nformation, go to www.micrel.com . downloaded from: http:///
micrel, inc. ksz8081mlx august 19 , 2015 60 revision 1.3 micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944 - 0800 fax +1 (408) 474 - 1000 web http://www.micrel.com micrel , inc. is a leading global manufacturer of ic solutions for the worldwide high performance linear and power , lan, and timing & communications markets. the companys products include advanced mixed - signal, analog & power semiconductors; high - performance com munication, clock management, mems - based clock oscillators & crystal - less clock generators, ethernet switches, and physical layer transceiver ics. company customers include leading manufacturers of enterprise, consumer, industrial, mobile, telecommunications, automotive, and comp uter products. corporation headquarters and state - of - the - art waf er fabrication facilities are located in san jose, ca, with regional sales and support offices and advanced technology design centers situated throughout the americas, europe, and asia. additionally, the company maintains an extensive network of distribut ors and reps worldwide. micrel makes no representations or warranties with respect to the accuracy or completenes s of the inf ormation furnished in this data sheet. this information is not intended as a warranty and micrel does not assume responsibility for its use. micrel reserves the right to change circuitry, specifications and descriptions at any time without notice. no license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this document. e xcept as provided in micrels terms and conditions of sale for such products, micrel assumes no li ability whatsoever, and micrel disclaims any express or implied warranty relating to the sale and/or use of mi crel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright , or other intellectual property right. micrel products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. life support devices or systems are devices or sy stems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. a purchasers use or sale of micrel products for use in life support appliances, devices or s ystems is a purchasers own risk and purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 20 12 micrel, incorporated. downloaded from: http:///

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